The Implementation of a VHDL-AMS to SPICE Converter
Journal of VLSI Signal Processing Systems - Mixed-signal design issues
The Implementation of a VHDL-AMS to SPICE Converter
Analog Integrated Circuits and Signal Processing - Special issue on mixed-signal design issues
Proceedings of the conference on Design, automation and test in Europe
Instruction-level DFT for testing processor and IP cores in system-on-a-chip
Proceedings of the 38th annual Design Automation Conference
Embedded software-based self-testing for SoC design
Proceedings of the 39th annual Design Automation Conference
Debugging Hardware Designs Using a Value-Based Model
Applied Intelligence
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Journal of Electronic Testing: Theory and Applications
Functionally Testable Path Delay Faults on a Microprocessor
IEEE Design & Test
Instruction-Based Self-Testing of Processor Cores
Journal of Electronic Testing: Theory and Applications
Test Program Synthesis for Path Delay Faults in Microprocessor Cores
ITC '00 Proceedings of the 2000 IEEE International Test Conference
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs
IEEE Design & Test
Debugging VHDL Designs: Introducing Multiple Models and First Empirical Results
Applied Intelligence
A procedure for obtaining a behavioral description for the control logic of a non-linear pipeline
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation
Journal of Electronic Testing: Theory and Applications
Debugging VHDL designs using temporal process instances
IEA/AIE'2003 Proceedings of the 16th international conference on Developments in applied artificial intelligence
Integration, the VLSI Journal - Special issue: Embedded cryptographic hardware
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors
IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Reconfigurable Hardware Architecture for Compact and Efficient Stochastic Neuron
IWANN '03 Proceedings of the 7th International Work-Conference on Artificial and Natural Neural Networks: Part II: Artificial Neural Nets Problem Solving Methods
International Journal of Parallel Programming - Special issue on the 19th international symposium on computer architecture and high performance computing (SBAC-PAD 2007)
Using genetic programming and high level synthesis to design optimized datapath
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
VECPAR'02 Proceedings of the 5th international conference on High performance computing for computational science
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences
Journal of Electronic Testing: Theory and Applications
Efficient hardware for modular exponentiation using the sliding-window method
International Journal of High Performance Systems Architecture
A hardware architecture for subtractive clustering
International Journal of High Performance Systems Architecture
Reconfigurable hardware to radionuclide identification using subtractive clustering
ICA3PP'11 Proceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part II
A parallel architecture for DNA matching
ICA3PP'11 Proceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part II
Hardware for modular exponentiation suitable for smart cards
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
A massively parallel hardware for modular exponentiations using the m-ary method
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II
A fuzzy logic-based video subtitle and caption coloring system
Advances in Fuzzy Systems
Functional test-sequence grading at register-transfer level
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable hardware for fuzzy controller
International Journal of High Performance Systems Architecture
Hardware implementation of subtractive clustering for radionuclide identification
Integration, the VLSI Journal
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From the Publisher:Here's the new second edition of the authoritative reference engineers need to guide them through the use of VHDL hardware description language in the analysis, simulation, and modeling of complicated microelectronic circuits. You'll find extensive new material to bring the guide fully up to date with the new VHDL93 standard, including new chapters on design flow, interfacing, modeling, and timing. Extensive appendixes, including ones on logic synthesis and CPU description styles, provide up-to-date information on the use of VHDL in design. The number and depth of its relevant and practical examples and problems is what sets this edition apart from other VHDL texts.