Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Integration of partial scan and built-in self-test
Journal of Electronic Testing: Theory and Applications - Special issue on partial scan methods
Generation of High Quality Tests for Robustly Untestable Path Delay Faults
IEEE Transactions on Computers
Testable path delay fault cover for sequential circuits
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
VHDL: Analysis and Modeling of Digital Systems
VHDL: Analysis and Modeling of Digital Systems
Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An almost full-scan BIST solution-higher fault coverage and shorter test application time
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Identifying Redundant Path Delay Faults in Sequential Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Instruction Randomization Self Test For Processor Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Functional Testing of Microprocessors
IEEE Transactions on Computers
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical test generation under architectural level functional constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay fault coverage, test set size, and performance trade-offs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Instruction-level DFT for testing processor and IP cores in system-on-a-chip
Proceedings of the 38th annual Design Automation Conference
Embedded software-based self-testing for SoC design
Proceedings of the 39th annual Design Automation Conference
Test of future system-on-chips
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Embedded Software-Based Self-Test for Programmable Core-Based Designs
IEEE Design & Test
A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
Designing Self Test Programs for Embedded DSP Cores
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Efficient techniques for transition testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Instruction-level test methodology for CPU core self-testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Software-based self-test methodology for crosstalk faults in processors
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Software-based self-test of processors under power constraints
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A Self Test Program Design Technique for Embedded DSP Cores
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On efficient generation of instruction sequences to test for delay defects in a processor
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors
IEICE - Transactions on Information and Systems
Instruction-based self-testing of delay faults in pipelined processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Exploiting MOEA to automatically geneate test programs for path-delay faults in microprocessors
Evo'08 Proceedings of the 2008 conference on Applications of evolutionary computing
Fast enhancement of validation test sets for improving the stuck-at fault coverage of RTL circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper addresses the problem of testing path delayfaults in a microprocessor core using its instruction set. We propose to self-test a processor core by running an automatically synthesized test program which can achieve a high path delay fault coverage. This paper discusses the method and the prototype software framework for synthesizing such a test program. Based on the processor'sinstruction set architecture, micro-architecture, RTL netlistas well as gate-level netlist on which the path delay faultsare modeled, the method generates deterministic tests (inthe form of instruction sequences) by cleverly combiningstructural and instruction-level test generation techniques.The experimental results for two microprocessors indicatethat the test instruction sequences can be successfully generated for a high percentage of testable path delay faults.