Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Evolutionary Algorithms for Solving Multi-Objective Problems
Evolutionary Algorithms for Solving Multi-Objective Problems
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
Multiple Objective Optimization with Vector Evaluated Genetic Algorithms
Proceedings of the 1st International Conference on Genetic Algorithms
Test Program Synthesis for Path Delay Faults in Microprocessor Cores
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Delay Defect Characteristics and Testing Strategies
IEEE Design & Test
Instruction-Based Delay Fault Self-Testing of Processor Cores
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs
IEEE Design & Test
TranGen: a SAT-based ATPG for path-oriented transition faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Automatic Generation of Instructions to Robustly Test Delay Defects in Processors
ETS '07 Proceedings of the 12th IEEE European Test Symposium
On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Proceedings of the conference on Design, automation and test in Europe
Function-based compact test pattern generation for path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evolving assembly programs: how games help microprocessor validation
IEEE Transactions on Evolutionary Computation
A review of multiobjective test problems and a scalable test problem toolkit
IEEE Transactions on Evolutionary Computation
IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient identification of (critical) testable path delay faults using decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Feedback-based coverage directed test generation: an industrial evaluation
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Coverage-Directed Test Generation Automated by Machine Learning -- A Review
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper presents an innovative approach for the generation of test programs detecting path-delay faults in microprocessors. The proposed method takes advantage of the multiobjective implementation of a previously devised evolutionary algorithm and exploits both gate- and RT-level descriptions of the processor: the former is used to build Binary Decision Diagrams (BDDs) for deriving fault excitation conditions; the latter is used for the automatic generation of test programs able to excite and propagate fault effects, based on a fast RTL simulation. Experiments on an 8-bit microcontroller show that the proposed method is able to generate suitable test programs more efficiently compared to existing approaches.