Exploiting MOEA to automatically geneate test programs for path-delay faults in microprocessors
Evo'08 Proceedings of the 2008 conference on Applications of evolutionary computing
Test generation for clock-domain crossing faults in integrated circuits
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Delay testing is mandatory for guaranteeing the correct behavior of today's high-performance microprocessors. Several methodologies have been proposed to tackle this issue resorting to additional hardware or to software self-test techniques. Software techniques are particularly promising as they resort to Assembly programs in normal mode of operation, without requiring circuit modifications; however, the problem of generating effective and efficient test programs for path-delay fault detection is still open. This paper presents an innovative approach for the generation of path-delay self-test programs for microprocessors, based on an evolutionary algorithm and on ad-hoc software simulation/hardware emulation heuristic techniques. Experimental results show how the proposed methodology allows generating suitable test programs in reasonable times.