Instruction-Based Delay Fault Self-Testing of Processor Cores

Authors:
Virendra Singh;Michiko Inoue;Kewal K. Saluja;Hideo Fujiwara
Affiliations:
-;-;-;-
Venue:
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Year:
2004

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Cited 3

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Abstract

This paper proposes an efficient methodology of delayfault testing of processor cores using its instruction set.These test vectors can be applied in the functional mode ofoperation, hence, self-testing of processor core becomespossible. Path delay fault model is used. The proposedapproach uses a graph theoretic model (represented as anInstruction Execution Graph) of the datapath and a finitestate machine model of the controller for the elimination offunctionally untestable paths at the early stage withoutlooking into the circuit details and extraction of constraintsfor the paths that can potentially be tested. Parwanprocessor is used to demonstrate the effectiveness of ourmethod.