Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Instruction-level DFT for testing processor and IP cores in system-on-a-chip
Proceedings of the 38th annual Design Automation Conference
VHDL: Analysis and Modeling of Digital Systems
VHDL: Analysis and Modeling of Digital Systems
A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
Test Program Synthesis for Path Delay Faults in Microprocessor Cores
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Efficient Template Generation for Instruction-Based Self-Test of Processor Cores
ATS '04 Proceedings of the 13th Asian Test Symposium
Software-based self-testing methodology for processor cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we propose a design for testability method for test programs of software-based self-test using test program templates. Software-based self-test using templates has a problem of error masking where some faults detected in a test generation for a module are not detected by the test program synthesized from the test. The proposed method achieves 100% template level fault efficiency, that is, it completely avoids the error masking. Moreover, the proposed method has no performance degradation (adds only observation points) and enables at-speed testing.