Software-based diagnosis for processors
Proceedings of the 39th annual Design Automation Conference
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Journal of Electronic Testing: Theory and Applications
Embedded Software-Based Self-Test for Programmable Core-Based Designs
IEEE Design & Test
Instruction-Based Self-Testing of Processor Cores
Journal of Electronic Testing: Theory and Applications
A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
Test data compression and test time reduction using an embedded microprocessor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores
Journal of Electronic Testing: Theory and Applications
BIST Technique by Equally Spaced Test Vector Sequences
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Low-Cost Software-Based Self-Testing of RISC Processor Cores
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Software-Based Self-Testing of Embedded Processors
IEEE Transactions on Computers
A constraint-based solution for on-line testing of processors embedded in real-time applications
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Software-based self-test methodology for crosstalk faults in processors
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Optimal periodic testing of intermittent faults in embedded pipelined processor applications
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Software-based self-testing of microprocessors
Journal of Systems Architecture: the EUROMICRO Journal
Systematic software-based self-test for pipelined processors
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
A System-layer Infrastructure for SoC Diagnosis
Journal of Electronic Testing: Theory and Applications
Software-based self-testing with multiple-level abstractions for soft processor cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A hybrid software-based self-testing methodology for embedded processor
Proceedings of the 2008 ACM symposium on Applied computing
Antirandom testing: a distance-based approach
VLSI Design
Scheduling Power-Constrained Tests through the SoC Functional Bus
IEICE - Transactions on Information and Systems
Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors
IEICE - Transactions on Information and Systems
Automatic constraint based test generation for behavioral HDL models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Instruction-based self-testing of delay faults in pipelined processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Using introspective software-based testing for post-silicon debug and repair
Proceedings of the 47th Design Automation Conference
Reducing the storage requirements of a test sequence by using a background vector
Proceedings of the Conference on Design, Automation and Test in Europe
Systematic software-based self-test for pipelined processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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At-speed testing of gigahertz processors using external testers may not be technically and economically feasible. Hence, there is an emerging need for low-cost high-quality self-test methodologies that can be used by processors to test themselves at-speed. Currently, built-in self-test (BIST) is the primary self-test methodology available. While memory BIST is commonly used for testing embedded memory cores, complex logic designs such as microprocessors are rarely tested with logic BIST. In this paper, we first analyze the issues associated with current hardware-based logic-BIST methodologies by applying a commercial logic-BIST tool to two processor cores. We then propose a new software-based self-testing methodology for processors, which uses a software tester embedded in the processor memory as a vehicle for applying structural tests. The software tester consists of programs for test generation and test application. Prior to the test, structural tests are prepared for processor components in the form of self-test signatures. During the process of self-test, the test generation program expands the self-test signatures into test sets and the test application program applies the tests to the components under test at the speed of the processor. Application of the novel software-based self-test method demonstrates its significant cost/fault coverage benefits and its ability to apply at-speed test while alleviating the need for high-speed testers