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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Computers and Electrical Engineering
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Systems-on-a-chip (SOCs) with many complex intellectual property cores require a large volume of data for manufacturing test. The computing power of the embedded processor in a SOC can be used to test the cores within the chip boundary, reducing the test time and memory requirements. This paper discusses techniques that use the computing power of the embedded processor in a more sophisticated way. The processor can generate and reuse random numbers to construct test patterns and selectively apply only those patterns that contribute to the fault coverage, significantly reducing the pattern generation time, the total number of test applications and, hence, the test time. It can also apply deterministic test patterns that have been compressed using the characteristics of the random patterns as well as those of the deterministic patterns themselves, which leads to high compression of test data. We compare three fast run-length coding schemes which are easily implemented and effective for test-data compression. We also demonstrate the effectiveness of the proposed approach by applying it to some benchmark circuits and by comparing it with other available techniques.