An Efficient Method for Compressing Test Data

Memory fault diagnosis by syndrome compression

Proceedings of the conference on Design, automation and test in Europe

Selective-run built-in self-test using an embedded processor

Proceedings of the 12th ACM Great Lakes symposium on VLSI

Embedded test control schemes for compression in SOCs

Proceedings of the 39th annual Design Automation Conference

A Method for Compressing Test Data Based on Burrows-Wheeler Transformation

IEEE Transactions on Computers

Deterministic Built-in Pattern Generation for Sequential Circuits

Journal of Electronic Testing: Theory and Applications

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

Journal of Electronic Testing: Theory and Applications

Test vector decompression via cyclical scan chains and its application to testing core-based designs

ITC '98 Proceedings of the 1998 IEEE International Test Conference

4.1 COMPACT: A Hybrid Method for Compressing Test Data

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

19.1 Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

Scan Test Sequencing Hardware for Structural Test

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Test data compression and test time reduction using an embedded microprocessor

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power

Matrix-based software test data decompression for systems-on-a-chip

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip

Two dimensional reordering of functional test data for compression by ATE

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI

Application of Arithmetic Coding to Compression of VLSI Test Data

IEEE Transactions on Computers