An Efficient Method for Compressing Test Data
Proceedings of the IEEE International Test Conference
Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Minimizing Test Time by Exploiting Parallelism in Macro Test
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
The Test and Debug Features of the AMD-K7TM Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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This paper introduces a new hardware implementation for scan test sequencing within a tester. Insteadof providing a monolithic scan memory with linearreadback capabilities, the proposed test architecture uses dedicated scan test sequencing hardwareto provide "on-the-fly" scan test sequencing. Theapproach is aimed not only at providing a more flexible test hardware solution, but at reducing the costof structural test by significantly reducing scanmemory size requirements.