Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Introducing Core-Based System Design
IEEE Design & Test
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
An Efficient Method for Compressing Test Data
Proceedings of the IEEE International Test Conference
Modifying User-Defined Logic for Test Access to Embedded Cores
Proceedings of the IEEE International Test Conference
4.1 COMPACT: A Hybrid Method for Compressing Test Data
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Scan Vector Compression/Decompression Using Statistical Coding
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Test Data Compression for System-on-a-Chip Using Golomb Codes
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Compression Technique for Interactive BIST Application
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
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This paper presents novel control schemes for testing embedded cores in a system on a chip (SOC). It converts a traditional BIST scheme into an externally controllable scheme to achieve a high test quality within optimal test execution time without inserting test points. The scheme promotes design and test reuse without revealing IP information.