Text compression
Data structures using C
Arithmetic coding for data compression
Communications of the ACM
Introduction to data compression (2nd ed.)
Introduction to data compression (2nd ed.)
Elements of Data Compression
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Matrix-Based Test Vector Decompression Using an Embedded Processor
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
An Efficient Method for Compressing Test Data
Proceedings of the IEEE International Test Conference
Test Requirements for Embedded Core-Based Systems and IEEE P1500
Proceedings of the IEEE International Test Conference
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Deterministic Test Vector Decompression in Software Using Linear Operations
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
ATE-Amenable Test Data Compression with No Cyclic Scan
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Compression of VLSI Test Data by Arithmetic Coding
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Test set compaction algorithms for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variable-length input Huffman coding for system-on-a-chip test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Concurrent core test for SOC using shared test set and scan chain disable
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs
IEEE Transactions on Computers
Test data compression for noc based socs using binary arithmetic operations
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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This paper proposes arithmetic coding for application to data compression for VLSI testing. The use of arithmetic codes results in a codeword whose length is close to the optimal value (as predicted by entropy in information theory), thus achieving a higher compression. Previous techniques (such as those based on Huffman or Golomb coding) result in optimal codes for data sets in which the probability model of the symbols satisfies specific requirements. This paper shows empirically and analytically that Huffman and Golomb codes can result in a large difference between the bound established by the entropy and the attained compression; therefore, the worst-case difference is studied using information theory. Compression results for arithmetic coding are presented using ISCAS benchmark circuits; a practical integer implementation of arithmetic coding/decoding and an analysis of its deviation from the entropy bound are pursued. A software implementation is proposed using embedded DSP cores. In the experimental evaluation, fully specified test vectors and test cubes from two different ATPG programs are utilized. The implications of arithmetic coding on manufacturing test using an ATE are also investigated.