Evaluation of heuristic techniques for test vector ordering
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Evaluation of Error-Resilience for Reliable Compression of Test Data
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Two dimensional reordering of functional test data for compression by ATE
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Application of Arithmetic Coding to Compression of VLSI Test Data
IEEE Transactions on Computers
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This paper deals with a novel data compression technique for Automatic Test Equipment (ATE). A new correlation extraction technique is presented which allows spanning the compressed test data over the memory of multiple ATE channels. After reordering, vector processing is executed on a columnwise basis such that bits in the same position of all vectors are simultaneously provided to each pin of the head. Differentiation which is commonly used to extract correlation among vectors is not required in the proposed technique. Several ATE issues related to memory utilization, off-chip compression/decompression, decompression circuitry area overhead (inclusive of the area of the Cyclic-Scan-Register, CSR), and the entropy of test data (as figure of merit for correlation extraction) are analyzed. Experimental results for combinational and sequential benchmark circuits are presented to substantiate the validity of the proposed technique for an ATE environment.