Application of Arithmetic Coding to Compression of VLSI Test Data
IEEE Transactions on Computers
DELTA '06 Proceedings of the Third IEEE International Workshop on Electronic Design, Test and Applications
Survey of Test Vector Compression Techniques
IEEE Design & Test
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multiscan-based Test Data Compression Using UBI Dictionary and Bitmask
ATS '11 Proceedings of the 2011 Asian Test Symposium
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Network-on-chip (NoC) is the most effective communication structure for System-on-Chip (SoC) components. Test data compression is essential to reduce test data volume, to decreases test costs. In this paper, a test compression and decompression solution is proposed based on binary arithmetic operations. Experimental results for full scan test data set of ISCAS'89 benchmarks are demonstrated. The major advantages include high compression ratio and a low cost decoder. It is observed that the proposed compression method achieves a compression ratio as high as 93.56% for ISCAS'89 benchmarks.