Test data compression for noc based socs using binary arithmetic operations
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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Since Systems-on-chip (SoCs) keep on being more and more complex, test data compression has become essential to reduce test costs. In particular, a common technique for reducing test time is to use multiple scan chains. Nevertheless, this possibility is limited by the number of available ATE (Automatic Test Equipment) channels. In this context, horizontal compression allows to fit the number of available ATE channels with the number of scan chains. But to achieve compression, these methods rely on the presence of don't care bits (X's) in the test sequences. Therefore, the length of these sequences is significantly greater than ones with fully specified bits. Conversely, serialization based methods allow to use fully specified test sequences, that are significantly smaller. This paper first presents a new method for horizontal test data compression and secondly proposes an answer to the question: is there really a benefit in terms of test application time (TAT) and test data volume of using compression instead of a simple serialization of test data?