Proceedings of the conference on Design, automation and test in Europe
Selective-run built-in self-test using an embedded processor
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
Proceedings of the 39th annual Design Automation Conference
Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test
Journal of Electronic Testing: Theory and Applications
Test Resource Partitioning for SOCs
IEEE Design & Test
A novel scan architecture for power-efficient, rapid test
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Test application time and volume compression through seed overlapping
Proceedings of the 40th annual Design Automation Conference
IEEE Transactions on Computers
Test data compression using dictionaries with selective entries and fixed-length indices
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test-decompression mechanism using a variable-length multiple-polynomial LFSR
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test data compression and test time reduction using an embedded microprocessor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
CircularScan: A Scan Architecture for Test Cost Reduction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes
Journal of Electronic Testing: Theory and Applications
Combining dictionary coding and LFSR reseeding for test data compression
Proceedings of the 41st annual Design Automation Conference
Fast and energy-frugal deterministic test through efficient compression and compaction techniques
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
A Technique for High Ratio LZW Compression
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Evaluation of Error-Resilience for Reliable Compression of Test Data
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Using MUXs Network to Hide Bunches of Scan Chains
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Journal of Electronic Testing: Theory and Applications
Two dimensional reordering of functional test data for compression by ATE
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Enhancing error resilience for reliable compression of VLSI test data
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Synchronization overhead in SOC compressed test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Application of Arithmetic Coding to Compression of VLSI Test Data
IEEE Transactions on Computers
Frugal linear network-based test decompression for drastic test cost reductions
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Design space exploration for aggressive test cost reduction in CircularScan architectures
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A cocktail approach on random access scan toward low power and high efficiency test
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Efficient test-data compression for IP cores using multilevel Huffman coding
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Optimized integration of test compression and sharing for SOC testing
Proceedings of the conference on Design, automation and test in Europe
Optimal Selective Huffman Coding for Test-Data Compression
IEEE Transactions on Computers
Test data compression scheme based on variable-to-fixed-plus-variable-length coding
Journal of Systems Architecture: the EUROMICRO Journal
EURASIP Journal on Applied Signal Processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Low cost scan test by test correlation utilization
Journal of Computer Science and Technology
A Test Data Compression Scheme for Reducing Power Based on OLELC and NBET
ICIC '08 Proceedings of the 4th international conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications - with Aspects of Theoretical and Methodological Issues
Multilevel-Huffman test-data compression for IP cores with multiple scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Architecture of Embedded Decompressor with Reconfigurability for Test Compression
IEICE - Transactions on Information and Systems
A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs
IEICE - Transactions on Information and Systems
Scan-chain partition for high test-data compressibility and low shift power under routing constraint
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test Data Compression Using Multi-dimensional Pattern Run-length Codes
Journal of Electronic Testing: Theory and Applications
Computers and Electrical Engineering
Reducing the storage requirements of a test sequence by using a background vector
Proceedings of the Conference on Design, Automation and Test in Europe
Test data compression using alternating variable run-length code
Integration, the VLSI Journal
Test data compression using efficient bitmask and dictionary selection methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Capture-power-aware test data compression using selective encoding
Integration, the VLSI Journal
Test data compression based on geometric shapes
Computers and Electrical Engineering
Test Data Compression Using Selective Sparse Storage
Journal of Electronic Testing: Theory and Applications
Test data compression using interval broadcast scan for embedded cores
Microelectronics Journal
A new scheme of test data compression based on equal-run-length coding (ERLC)
Integration, the VLSI Journal
Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs
Proceedings of the International Conference on Computer-Aided Design
Deterministic test vector compression / decompression using an embedded processor
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
Test data compression using four-coded and sparse storage for testing embedded core
ICA3PP'10 Proceedings of the 10th international conference on Algorithms and Architectures for Parallel Processing - Volume Part II
A modified scheme for simultaneous reduction of test data volume and testing power
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Test data compression for noc based socs using binary arithmetic operations
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
FPGA bitstream compression and decompression using LZ and golomb coding (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Scan power reduction for linear test compression schemes through seed selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding
Journal of Electronic Testing: Theory and Applications
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We present a new test-data compression method and decompression architecture based on variable-to-variable-length Golomb codes. The proposed method is especially suitable for encoding precomputed test sets for embedded cores in a system-on-a-chip (SoC). The major advantages of Golomb coding of test data include very high compression, analytically predictable compression results, and a low-cost and scalable on-chip decoder. In addition, the novel interleaving decompression architecture allows multiple cores in an SoC to be tested concurrently using a single automatic test equipment input-output channel. We demonstrate the effectiveness of the proposed approach by applying it to the International Symposium on Circuits and Systems' benchmark circuits and to two industrial production circuits. We also use analytical and experimental means to highlight the superiority of Golomb codes over run-length codes