On the effects of test compaction on defect coverage
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
IEEE Transactions on Computers
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
XPAND: An Efficient Test Stimulus Compression Technique
IEEE Transactions on Computers
Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-Transition Test Pattern Generation for BIST-Based Applications
IEEE Transactions on Computers
UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting
IEEE Design & Test
On capture power-aware test data compression for scan-based testing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories
IEEE Design & Test
Low-power scan operation in test compression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test Data Compression Using Multi-dimensional Pattern Run-length Codes
Journal of Electronic Testing: Theory and Applications
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power scan testing and test data compression for system-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A unified approach to reduce SOC test data volume, scan power and testing time
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variable-length input Huffman coding for system-on-a-chip test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A modified scheme for simultaneous reduction of test data volume and testing power
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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This paper presents a unified test data compression approach, which simultaneously reduces test data volume, scan power consumption and test application time for a system-on-a-chip (SoC). The proposed approach is based on the use of alternating variable run-length (AVR) codes for test data compression. A formal analysis of scan power consumption and test application time is presented. The analysis showed that a careful mapping of the don't-cares in pre-computed test sets to 1s and 0s led to significant savings in peak and average power consumption, without requiring slower scan clocks. The proposed technique also reduced testing time compared to a conventional scan-based scheme. The alternating variable run-length codes can efficiently compress the data streams that are composed of both runs 0s and 1s. The decompression architecture was also presented in this paper. Experimental results for ISCAS'89 benchmark circuits and a production circuit showed that the proposed approach greatly reduced test data volume and scan power consumption for all cases.