New test data decompressor for low power applications
Proceedings of the 44th annual Design Automation Conference
Journal of Electronic Testing: Theory and Applications
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations
Journal of Electronic Testing: Theory and Applications
An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR
Journal of Electronic Testing: Theory and Applications
Low-power scan operation in test compression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power supply noise reduction for at-speed scan testing in linear-decompression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test data compression using alternating variable run-length code
Integration, the VLSI Journal
On reducing test power and test volume by selective pattern compression schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping
Journal of Electronic Testing: Theory and Applications
Achieving low capture and shift power in linear decompressor-based test compression environment
Microelectronics Journal
Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs
Proceedings of the International Conference on Computer-Aided Design
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This paper presents a new low-power test-data-compression scheme based on linear feedback shift register (LFSR) reseeding. A drawback of compression schemes based on LFSR reseeding is that the unspecified bits are filled with random values, which results in a large number of transitions during scan-in, thereby causing high-power dissipation. A new encoding scheme that can be used in conjunction with any LFSR-reseeding scheme to significantly reduce test power and even further reduce test storage is presented. The proposed encoding scheme acts as the second stage of compression after LFSR reseeding. It accomplishes two goals. First, it reduces the number of transitions in the scan chains (by filling the unspecified bits in a different manner). Second, it reduces the number of specified bits that need to be generated via LFSR reseeding. Experimental results indicate that the proposed method significantly reduces test power and in most cases provides greater test-data compression than LFSR reseeding alone