Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Inserting Test Points to Control Peak Power During Scan Testing
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
An Input Control Technique for Power Reduction in Scan Circuits During Test Application
ATS '99 Proceedings of the 8th Asian Test Symposium
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Scan Power Reduction Through Test Data Transition Frequency Analysis
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Reducing Average and Peak Test Power Through Scan Chain Modification
Journal of Electronic Testing: Theory and Applications
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Reducing Power Dissipation during Test Using Scan Chain Disable
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Test Power Reduction through Minimization of Scan Chain Transitions
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Test Vector Modification for Power Reduction during Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Controlling Peak Power During Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Aggressive Test Power Reduction Through Test Stimuli Transformation
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Design of Routing-Constrained Low Power Scan Chains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
On Low-Capture-Power Test Generation for Scan Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Reduction of Instantaneous Power by Ripple Scan Clocking
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Jump Scan: A DFT Technique for Low Power Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Partial Gating Optimization for Power Reduction During Test Application
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Test Cost Reduction Using Partitioned Grid Random Access Scan
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Logic BISTWith Scan Chain Segmentation
ITC '04 Proceedings of the International Test Conference on International Test Conference
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction
IEEE Transactions on Computers
Low-power scan design using first-level supply gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Scan-based cores impose considerable test power challenges due to excessive switching activity during shift cycles. The consequent test power constraints force system-on-chip (SOC) designers to sacrifice parallelism among core tests, as exceeding power thresholds may damage the chip being tested. Reduction of test power for SOC cores can thus increase the number of cores that can be tested in parallel, improving significantly SOC test application time. In this paper, we propose a scan chain modification technique that inserts logic gates on the scan path. The consequent beneficial test data transformations are utilized to reduce the scan chain transitions during shift cycles and hence test power. We introduce a matrix band algebra that models the impact of logic gate insertion between scan cells on the test stimulus and response transformations realized. As we have successfully modeled the response transformations as well, the methodology we propose is capable of truly minimizing the overall test power. The test vectors and responses are analyzed in an intertwined manner, identifying the best possible scan chain modification, which is realized at minimal area cost. Experimental results justify the efficacy of the proposed methodology as well.