Scan Power Minimization through Stimulus and Response Transformations
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Low cost scan test by test correlation utilization
Journal of Computer Science and Technology
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
Excessive switching activity during shift cycles in scan-basedcores imposes considerable test power challenges. To ensure rapidand reliable test of SOCs, we propose a scan chain modificationmethodology that transforms the stimuli to be inserted to the scanchain through logic gate insertion between scan cells, reducingscan chain transitions. We introduce a novel matrix band algebra toformulate the impact of scan chain modifications on test stimulitransformations. Based on this analysis, we develop algorithms fortransforming a set of test vectors into power-optimal test stimulithrough cost-effective scan chain modifications. Experimentalresults show that scan-in power reductions exceeding 90% for testvectors and 99.5% for test cubes can be attained by the proposedmethodology.