Test Cost Reduction Using Partitioned Grid Random Access Scan

Authors:
Dong Hyun Baik;Kewal K. Saluja
Affiliations:
University of Wisconsin - Madison;University of Wisconsin - Madison
Venue:
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Year:
2006

Citing 0
Cited 3

Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations

Journal of Electronic Testing: Theory and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability
Single cycle access structure for logic test

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

The random access scan (RAS) has the ability to address major problems associated with serial-scan method. A practically implementable RAS test architecture called Progressice Random Access Scan (PRAS) was introduced earlier. This paper proposes a generalized architecture for the PRAS. We show that the generalized PRAS architecture offers two orders of magnitude gains in test application time over traditional serial scan and is superior to multiple serial scan in terms of the use of tester channels.