Random Access Scan: A solution to test power, test data volume and test time
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Test Cost Reduction Using Partitioned Grid Random Access Scan
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
PRDC '05 Proceedings of the 11th Pacific Rim International Symposium on Dependable Computing
A cocktail approach on random access scan toward low power and high efficiency test
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Test Data Compression Based on Clustered Random Access Scan
ATS '06 Proceedings of the 15th Asian Test Symposium
Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A BIST TPG for low power dissipation and high fault coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Localized random access scan: towards low area and routing overhead
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A Scheme of Test Pattern Generation Based on Reseeding of Segment-Fixing Counter
ICYCS '08 Proceedings of the 2008 The 9th International Conference for Young Computer Scientists
WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Dynamic scan chain partitioning for reducing peak shift power during test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On Minimization of Test Application Time for RAS
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An automatic test pattern generator for minimizing switching activity during scan testing activity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test pattern generation and clock disabling for simultaneous test time and power reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-Power Test Data Application in EDT Environment Through Decompressor Freeze
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes a new single cycle access test tructure for logic test. It eliminates the peak power consumption problem of conventional shift-based scan chains and reduces the activity during shift and capture cycles. This leads to more realistic circuit behavior during stuck-at and at-speed tests. It enables the complete test to run at much higher frequencies equal or close to the one in functional mode. It will be shown, that a lesser number of test cycles can be achieved compared to other published solutions. The test cycles per net based on a simple test pattern generator algorithm without test pattern compression is below 1 for larger designs and is independent of the design size. Results are compared to other published solutions on ISCAS'89 netlists. The structure allows an additional on-chip debugging signal visibility for each register. The method is backward compatible to full scan designs and existing test pattern generators and simulators can be used with a minor enhancement. It is shown how to combine the proposed solution with built-in self test (BIST) and massive parallel scan chains.