Single cycle access structure for logic test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper proposes a new BIST test pattern generation scheme based on random access scan architecture. In this scheme, segment-fixing strategy is used to BIST test pattern generator based on a counter, which can reduce the number of redundant test patterns, and improve the efficiency of test patterns generation. As random access scan mechanism is utilized in this scheme, only one scan cell needs to be updated when a new test pattern is fed to scan cells. Experimental results on ISCAS-89 benchmark show that the scheme can effectively reduce test data volume, test application time and test power consumption.