A New Approach to Test Generation and Test Compaction for Scan Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Single cycle access structure for logic test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Proposes a procedure for generating compact test sets with enhanced at-speed testing capabilities for scan circuits. Compaction refers here to a reduction in the test application time, while at-speed testing refers to the application of primary input sequences that contribute to the detection. of delay defects. The proposed procedure generates an initial test set that has a low test application time and consists of long sequences of primary input vectors applied consecutively. To construct this test set, the proposed procedure transforms a test sequence To for the nonscan circuit into a scan-based test by selecting an appropriate scan-in state and removing primary input vectors from To if they do not contribute to the fault coverage. If To contains long transfer sequences, several scan-based tests with long primary input sequences may be obtained by replacing transfer sequences in To with scan operations. This helps reduce the test application time further. We demonstrate through experimental results the advantages of this approach over earlier ones as a method for generating test sets with minimal test application time and long primary input sequences