Single cycle access structure for logic test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test compaction techniques for assertion-based test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The test application time of a scan circuit is a significant factor in the overall test cost of the circuit. Therefore, reducing the test application time is an important problem. The test application time of a test set for a scan circuit is determined by the sum of the number of scan shifts required for applying the test set and the number of primary input vectors in the test set. Compaction procedures that view a full-scan circuit as a combinational circuit reduce the number of test vectors, where a test vector consists of a scan vector and a primary input vector. However, this is not sufficient, and effective procedures must reduce the number of scan operations further than the combinational circuit view allows. Procedures to reduce the test application time by dropping scan operations and applying several primary input vectors between scan operations have been proposed earlier. The compaction procedures proposed in this work reduce the test application time further by using limited scan operations. Under a limited scan operation, the number of shifts is smaller than the length of a scan chain. Scan operations that cannot be dropped are replaced by limited scan operations under the proposed procedures.