Test Data Compression Based on Clustered Random Access Scan

Authors:
Yu Hu;Cheng Li;Jia Li;Yin-He Han;Xiao-Wei Li;Wei Wang;Hua-Wei Li;Laung-Terng(L. T) Wang;Xiao-Qing Wen
Affiliations:
Chinese Academy of Sciences;Chinese Academy of Sciences;Chinese Academy of Sciences;Chinese Academy of Sciences;Chinese Academy of Sciences;Chinese Academy of Sciences;Chinese Academy of Sciences;SynTest Technologies, Inc., Sunnyvale 94086, U.S.A.;Kyushu Institute of Technology, Japan
Venue:
ATS '06 Proceedings of the 15th Asian Test Symposium
Year:
2006

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System-on-Chip Test Architectures: Nanometer Design for Testability

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Single cycle access structure for logic test

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

We proposed a Clustered Random Access Scan (CRAS) architecture to reduce test data volume. CRAS makes use of the compatibility of the test stimuli to cluster the scan cells, and assigns every cluster a unique address. The compression ratio upper bound of CRAS is analyzed based on the random graph theory. Experimental results on ISCAS'89 benchmarks and two industry designs show that the proposed CRAS architecture can yield on average 67.3% reduction in test data volume, with reasonable area and routing overhead than scan design.