Localized random access scan: towards low area and routing overhead
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Single cycle access structure for logic test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Studies of Random-Access Scan (RAS) architecture have largely limited their scope to reduce test application time, test volume and test power to detect conventional stuck-at faults. In this paper we propose an enhanced RAS latch design for two pattern tests. The proposed latch is a minor modification of the RAS latch and is well suited for delayfault tests. In contrast, the traditional serial scan latch needs a major enhancement. As a result the RAS may offer a hardware advantage while the test time is nearly halved over the serial scan design. We demonstrate the test time advantage in this paper for various test sets for benchmark circuits and we argue that the advantage is even larger when test sets are generated for RAS architecture in mind, as well as by the exploitation of unspecified bits in test vectors.