An on-chip clock generation scheme for faster-than-at-speed delay testing
Proceedings of the Conference on Design, Automation and Test in Europe
Functional and partially-functional skewed-load tests
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Fixed-state tests for delay faults in scan designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Generation of mixed test sets for transition faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Flip-flop selection for partial enhanced scan to reduce transition test data volume
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Single cycle access structure for logic test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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At-speed testing is becoming crucial for modern very-large-scale-integration systems, which operate at clock speeds of hundreds of megahertz. In a scan-based test methodology, it is common to use a transition delay fault model for at-speed testing. The launching of the transition can be done either in the last cycle of scan shift [launch-off-shift (LOS)], or in a functional launch cycle that follows the scan shift and precedes the fast capture [launch-off-capture (LOC)]. The LOS technique offers significant advantages over the LOC in terms of coverage and pattern count, but since it requires the scan enable (SEN) signal to change state in the time period of one functional clock cycle, considerable engineering resources are required to close the timing on the SEN signal. Low-cost testers will not be able to provide the at-speed SEN signal as required by the LOS technique. We propose a scan-based at-speed methodology that generates "local" SEN signals that are guaranteed to switch in one functional clock cycle even when the external SEN signal does not change state at functional speed. Our technique is based on encapsulating the SEN control signal in the scan test data. A new scan cell, which is called the last transition generator, must be inserted in every scan chain for generating internal SEN signals. The proposed method is robust, practical, and readily implemented using commercial tools available today