OPMISR: the foundation for compressed ATPG vectors
Proceedings of the IEEE International Test Conference 2001
On Generating High Quality Tests for Transition Faults
ATS '02 Proceedings of the 11th Asian Test Symposium
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
The ATPG Conflict-Driven Scheme for High Transition Fault Coverage and Low Test Cost
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Test sets that contain both broadside and skewed-load tests are important for achieving the highest possible delay fault coverage for standard-scan circuits. Both types of tests can be represented as 〈s1 v1, s2 v2〉, where s1 and s2 are states, and v1 and v2 are primary input vectors. To facilitate the generation of a mixed test set that contains both broadside and skewed-load tests, this paper associates with s2 a property that can be used for estimating whether a skewed-load or a broadside test is more likely to exist with s2 in its second pattern. This paper uses this property for guiding a test generation procedure to consider only one of the two test types for most of the target faults.