Flip-flop selection for partial enhanced scan to reduce transition test data volume

Authors:
Songwei Pei;Huawei Li;Xiaowei Li
Affiliations:
State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, and Research Institute of Information Technology, Tsinghua University, Beijing, China;State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China;State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2012

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Abstract

We propose a flip-flop selection method to reduce the overall volume of transition delay test data, by replacing a small number of selected regular scan cells with enhanced scan cells. Relative measures are presented to reflect the gains when controlling a scan cell to a certain value, and guide the scan cell selection. Experimental results on larger IWLS 2005 benchmark circuits show that, to achieve the same fault coverage of the pure launch on capture (LOC) approach, the volume of test data can be reduced to a half on average by replacing only 1% of regular scan cells to enhanced scan cells. The transition delay fault coverage can also be improved using the proposed method with equally low area overhead.