A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits

Experiments on the synthesis and testability of non-scan finite state machines

EURO-DAC '92 Proceedings of the conference on European design automation

Clock grouping: a low cost DFT methodology for delay testing

DAC '94 Proceedings of the 31st annual Design Automation Conference

On primitive fault test generation in non-scan sequential circuits

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

Delay fault testing of IP-based designs via symbolic path modeling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Multiple Scan Chain Design for Two-Pattern Testing

Journal of Electronic Testing: Theory and Applications

On Using Twisted-Ring Counters for Test Set Embedding in BIST

Journal of Electronic Testing: Theory and Applications

BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms

IEEE Transactions on Computers

Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits

ATS '95 Proceedings of the 4th Asian Test Symposium

Gate delay fault test generation for non-scan circuits

EDTC '95 Proceedings of the 1995 European conference on Design and Test

Delay Fault Testing of Designs with Embedded IP Cores

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Using a Hierarchical DfT Methodology in High Frequency Processor Designs for Improved Delay Fault Testability

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Delay Testing with Clock Control: An Alternative to Enhanced Scan

ITC '97 Proceedings of the 1997 IEEE International Test Conference

On Achieving Complete Coverage of Delay Faults in Full Scan Circuits using Locally Available Lines

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Delay Fault Testing of IP-Based Designs Via Symbolic Path Modeling

ITC '99 Proceedings of the 1999 IEEE International Test Conference

A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

Layout-aware scan chain reorder for launch-off-shift transition test coverage

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique

Journal of Electronic Testing: Theory and Applications

Improved launch for higher TDF coverage with fewer test patterns

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Fastpath: a path-delay test generator for standard scan designs

ITC'94 Proceedings of the 1994 international conference on Test

On path delay testing in a standard scan environment

ITC'94 Proceedings of the 1994 international conference on Test

Flip-flop selection for partial enhanced scan to reduce transition test data volume

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

RTL analysis and modifications for improving at-speed test

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe

Design-for-testability for multi-cycle broadside tests by holding of state variables

ACM Transactions on Design Automation of Electronic Systems (TODAES)