ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Finding Defects with Fault Models
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Bit parallel test pattern generation for path delay faults
EDTC '95 Proceedings of the 1995 European conference on Design and Test
On test coverage of path delay faults
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Tutorial: Delay Fault Models and Coverage
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Segment delay faults: a new fault model
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Multiple Scan Chain Design for Two-Pattern Testing
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Testability Evaluation of Sequential Designs Incorporating the Multi-Mode Scannable Memory Element
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Layout-aware scan chain reorder for launch-off-shift transition test coverage
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Non-standard fault models often require the application of two-pattern testing. A fully-automated approach for generating a multiple scan chain-based architecture is presented so that two-pattern test sets generated for the combinational core can be applied to the sequential circuit. Test time and area overhead constraints are considered.