Multiple Scan Chain Design for Two-Pattern Testing

  • Authors:

  • llia Polian;Bernd Becker

  • Affiliations:

  • -;-

  • Venue:
  • VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
  • Year:
  • 2001

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Abstract

Non-standard fault models often require the application of two-pattern testing. A fully-automated approach for generating a multiple scan chain-based architecture is presented so that two-pattern test sets generated for the combinational core can be applied to the sequential circuit. Test time and area overhead constraints are considered.