Bit parallel test pattern generation for path delay faults

Authors:
M. Henftling;H. Wittman
Affiliations:
Institute of Electronic Design Automation, Department of Electrical Engineering, Technical University of Munich, 80290 Munich, Germany;Institute of Electronic Design Automation, Department of Electrical Engineering, Technical University of Munich, 80290 Munich, Germany
Venue:
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Year:
1995

Citing 7
Cited 8

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Abstract

A method to apply bit-parallel processing at all stages of robust and nonrobust test pattern generation for path delay faults is presented. Two different modes of bit-parallel processing are combined: fault parallel test pattern generation (FPTPG) and alternative parallel test pattern generation (APTPG). We discuss the problems that appear while exploiting bit-parallelity and we describe how to overcome them. Experimental results demonstrate a reduction of aborted faults and an acceleration up to a factor of nine.