Accelerated transition fault simulation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Parallel pattern fault simulation of path delay faults
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Random Pattern Testability of Delay Faults
IEEE Transactions on Computers
Path hashing to accelerate delay fault simulation
DAC '94 Proceedings of the 31st annual Design Automation Conference
Quality Determination for Gate Delay Fault Tests Considering Three-State Elements
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Bit parallel test pattern generation for path delay faults
EDTC '95 Proceedings of the 1995 European conference on Design and Test
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
| Hi-index | 14.98 |
An accelerated fault simulation approach for path delay faults is presented. The distinct features of the proposed fault simulation method consist in the application of parallel processing of patterns at all stages of the calculation procedure, its versatility to account for both robust and nonrobust decision of path delay faults, and its capability of efficiently maintaining large numbers of path faults to be simulated.