A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Parallel pattern fault simulation of path delay faults
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
An efficient delay test generation system for combinational logic circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A probabilistic testability measure for delay faults
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
On testing wave pipelined circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Delay Test Generation: A Hardware Perspective
Journal of Electronic Testing: Theory and Applications
Robust and Nonrobust Path Delay Fault Simulation by Parallel Processing of Patterns
IEEE Transactions on Computers
Generator choices for delay test
ATS '95 Proceedings of the 4th Asian Test Symposium
An efficient method for computing exact path delay fault coverage
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Some relationships between delay testing and stuck-open testing in CMOS circuits
EURO-DAC '90 Proceedings of the conference on European design automation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 14.98 |
In a computer system, the maximum allowable propagation delay of the combinational logic networks between latches is equal to the interval between the system clocks. The objective of delay testing is to guarantee that the delay of the manufactured network falls within specifications. Here, the capability of random patterns to detect slow paths in combinational logic is analyzed. Formulas that relate the length of the test to the desired test quality are derived.