Logic testing and design for testability
Logic testing and design for testability
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Random Pattern Testability of Delay Faults
IEEE Transactions on Computers
At-Speed Test is not Necessarily an AC Test
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Skewed-Load Transition Test: Part 1, Calculus
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Skewed-Load Transition Test: Part 2, Coverage
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Path Sensitization, Partial Boolean Difference, and Automated Fault Diagnosis
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
| Hi-index | 0.00 |
A broad-side delay test is a form of a scan-based delay test, where the first vector of the pair is scanned into the chain, and the second vector of the pair is the combinational circuit's response to this first vector. This delay test form is called "broad-side" since the second vector of the delay test pair is provided in a broad-side fashion, namely through the logic. This paper concentrates on generation of broadside delay test vectors; shows the results of experiments conducted on the ISCAS sequential benchmarks, and discusses some concerns of the broad-side delay test strategy.