Realistic fault modeling for VLSI testing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
From defects to failures: a view of dependable computing
ACM SIGARCH Computer Architecture News - Special Issue: Architectural Support for Operating Systems
High-Level Test Generation for VLSI
Computer
Computational Complexity of Controllability/Observability Problems for Combinational Circuits
IEEE Transactions on Computers
Cellular automata circuits for built-in self test
IBM Journal of Research and Development
Cellular Automata-Based Signature Analysis for Built-In Self-Test
IEEE Transactions on Computers
Testability of Software Components
IEEE Transactions on Software Engineering
On achieving a complete fault coverage for sequential machines using the transition fault model
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Observations on the Effects of Fault Manifestation as a Function of Workload
IEEE Transactions on Computers - Special issue on fault-tolerant computing
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
A multi level testability assistant for VLSI design
EURO-DAC '92 Proceedings of the conference on European design automation
VHDL switch level fault simulation
EURO-DAC '94 Proceedings of the conference on European design automation
On Fault Simulation for Synchronous Sequential Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Testable synthesis of high complex control devices
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
A formal non-heuristic ATPG approach
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Requirements-driven software test: a process-oriented approach
ACM SIGSOFT Software Engineering Notes
Partial scan design based on circuit state information
DAC '96 Proceedings of the 33rd annual Design Automation Conference
On Parallel Algorithms for Single-Fault Diagnosis in Fault Propagation Graph Systems
IEEE Transactions on Parallel and Distributed Systems
Easily Testable Realizations for Generalized Reed-Muller Expressions
IEEE Transactions on Computers
Cellular automata based synthesis of easily and fully testable FSMs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A New Design Method for Self-Checking Unidirectional Combinational Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
A Heuristic Measure to Maximize Detected Faults per Test
Journal of Electronic Testing: Theory and Applications
A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits
IEEE Transactions on Computers
Dedicated Circuits for the Generation of Windows in Image Processing Architectures
Journal of VLSI Signal Processing Systems
A New Class of Sequential Circuits with Combinational Test Generation Complexity
IEEE Transactions on Computers
A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
A non-scan DFT method at register-transfer level to achieve complete fault efficiency
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A true single-phase 8-bit adiabatic multiplier
Proceedings of the 38th annual Design Automation Conference
Fault Diagnosis in Mixed-Signal Low Testability System
Analog Integrated Circuits and Signal Processing
Test generation for acyclic sequential circuits with hold registers
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing
Journal of Electronic Testing: Theory and Applications
Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption
Journal of Electronic Testing: Theory and Applications
Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System
Journal of Electronic Testing: Theory and Applications
Algorithms for Automatic Test-Pattern Generation
IEEE Design & Test
A Testability Strategy for Microprocessor Architecture
IEEE Design & Test
IEEE Design & Test
A Behavioral Fault Simulator for Ideal
IEEE Design & Test
Progress in Design for Test: A Personal View
IEEE Design & Test
Notes on Multiple Input Signature Analysis
IEEE Transactions on Computers
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
Application of Homing Sequences to Synchronous Sequential Circuit Testing
IEEE Transactions on Computers
Fault Detection in Multiprocessor Systems and Array Processors
IEEE Transactions on Computers
Aliasing Error for a Mask ROM Built-In Self-Test
IEEE Transactions on Computers
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Training diploma students on ATE-related module
ATS '95 Proceedings of the 4th Asian Test Symposium
High-level test evaluation of asynchronous circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Generation of search state equivalence for automatic test pattern generation
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
16.2 A Structural Approach for Space Compaction for Concurrent Checking and BIST
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Test Structure Verification of Logical BIST: Problems and Solutions
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Non-Scan Design for Testability for Synchronous Sequential Circuits Based on Conflict Analysis
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Automatic Validation Methodology for Logic BIST in High Performance VLSI Design
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Efficient Hierarchical Approach to Test Generation for Digital Systems
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution
IEEE Transactions on Computers
Tools and devices supporting the pseudo-exhaustive test
EURO-DAC '90 Proceedings of the conference on European design automation
New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency
Journal of Electronic Testing: Theory and Applications
Efficient Design Diversity Estimation for Combinational Circuits
IEEE Transactions on Computers
Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Theorems for Fault Collapsing in Combinational Circuits
Journal of Electronic Testing: Theory and Applications
Co-Testing: Granting Testability in a Codesign Environment
Integrated Computer-Aided Engineering
Information Assurance: Dependability and Security in Networked Systems
Information Assurance: Dependability and Security in Networked Systems
Low-power scan testing for test data compression using a routing-driven scan architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A study on insuring the full reliability of finite state machine
ICCSA'03 Proceedings of the 2003 international conference on Computational science and its applications: PartII
Computational complexity in logic testing
INES'10 Proceedings of the 14th international conference on Intelligent engineering systems
System-level testability of hardware/software systems
ITC'94 Proceedings of the 1994 international conference on Test
What is the path to fast fault simulation?
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Enhancing random-pattern coverage of programmable logic arrays via masking technique
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Secure and testable scan design using extended de Bruijn graphs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Secure scan design using shift register equivalents against differential behavior attack
Proceedings of the 16th Asia and South Pacific Design Automation Conference
ALADIN: a multilevel testability analyzer for VLSI system design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
EGC'05 Proceedings of the 2005 European conference on Advances in Grid Computing
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