Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Logic testing and design for testability
Logic testing and design for testability
Practical implementation of charge recovering asymptotically zero power CMOS
Proceedings of the 1993 symposium on Research on integrated systems
Low-power digital systems based on adiabatic-switching principles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
AC-1: a clock-powered microprocessor
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
True single-phase adiabatic circuitry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier
ARVLSI '01 Proceedings of the 2001 Conference on Advanced Research in VLSI
A hybrid adiabatic content addressable memory for ultra low-power applications
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A true single-phase energy-recovery multiplier
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Will Moore's Law Be Sufficient?
Proceedings of the 2004 ACM/IEEE conference on Supercomputing
Charge-Recovery Computing on Silicon
IEEE Transactions on Computers
Fast, efficient, recovering, and irreversible
Proceedings of the 2nd conference on Computing frontiers
Boost Logic: A High Speed Energy Recovery Circuit Family
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A GHz-class charge recovery logic
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Energy-efficient low-latency 600 MHz FIR with high-overdrive charge-recovery logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-phase adiabatic logic family. Energy is supplied to the adiabatic circuitry via a sinusoidal power-clock waveform that is generated on-chip. In HSPICE simulations with post-layout extracted parasitics, our design functions correctly at clock frequencies exceeding 200 MHz. The total dissipation of the multiplier core and self-test circuitry approaches 130pJ per operation at 200MHz. Our 11,854-transistor chip has been fabricated in a 0.5&mgrm standard CMOS process with an active area of 0.470mm$^2$. Correct chip operation has been validated for operating frequencies up to 130MHz, the limit of our experimental setup. Measured dissipation correlates well with HSPICE simulations.