2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Signal entropy and the thermodynamics of computation
IBM Systems Journal
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Design and Evaluation of Adiabatic Arithmetic Units
Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems
True single-phase energy-recovering logic for low-power, high-speed VLSI
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Practical considerations of clock-powered logic
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A true single-phase 8-bit adiabatic multiplier
Proceedings of the 38th annual Design Automation Conference
Energy recovery for low-power CMOS
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Non-dissipative rail drivers for adiabatic circuits
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
A true single-phase energy-recovery multiplier
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Boost Logic: A High Speed Energy Recovery Circuit Family
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A GHz-class charge recovery logic
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Reversible P Systems to Simulate Fredkin Circuits
Fundamenta Informaticae - SPECIAL ISSUE MCU2004
Scheduling for reduced CPU energy
OSDI '94 Proceedings of the 1st USENIX conference on Operating Systems Design and Implementation
Reversible P Systems to Simulate Fredkin Circuits
Fundamenta Informaticae - SPECIAL ISSUE MCU2004
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