Practical implementation of charge recovering asymptotically zero power CMOS
Proceedings of the 1993 symposium on Research on integrated systems
Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic
Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic
A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI)
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Practical considerations of clock-powered logic
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Theory and practical implementation of harmonic resonant rail driver
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
A resonant clock generator for single-phase adiabatic systems
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Voltage-pulse driven harmonic resonant rail drivers for low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Implementing multiphase resonant clocking on a finite-impulse response filter
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Energy dissipation of CMOS circuits is becoming a major concern in the design of digital systems. Earlier, we presented a new form of CMOS charge recovery logic (SCRL), with an energy dissipation per operation that falls linearly with operating frequency, as opposed to the constant energy required for conventional CMOS circuits. These SCRL circuits, along with most adiabatic circuit techniques proposed to date, require a set of gradually swinging power supply rails that in effect force all charge transfers within the system to occur quasistatically. Proposals to date for generating these swinging rails have relied on a power MOSFET to gate the oscillation of an inductor, forming an RLC circuit. Even under ideal conditions, dissipation in this MOSFET degraded the overall energy savings of SCRL circuits from 1/T dependence to 1//spl radic/T. SCRL and other adiabatic circuits thus exhibited inferior overall energy saving performance when compared with supply voltage scaling of conventional CMOS circuits. In this paper, we present a technique for generating the required rail waveforms without the series power MOSFET to gate the inductor. This new rail driver circuit relies on adding multiple harmonics of the base frequency to generate a rail waveform of any desired shape. Our Harmonic Rail Driver (HRD) can be built using only passive reactive components or by using correctly trimmed transmission line segments. It is non-dissipative to within the achievable Q's of these components. Using HRDs to power and control SCRL circuits, we restore the overall dissipation of SCRL circuits to its attractive 1/T dependence.