The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Practical implementation of charge recovering asymptotically zero power CMOS
Proceedings of the 1993 symposium on Research on integrated systems
A sub-CV2 pad driver with 10 ns transition time
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Energy Considerations in Multichip-Module Based Multiprocessors
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Non-dissipative rail drivers for adiabatic circuits
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Energy recovery techniques for cmos microprocessor design
Energy recovery techniques for cmos microprocessor design
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Recovering and reusing circuit energies that would otherwise be dissipated as heat can reduce the power dissipated by a VLSI chip. To accomplish this requires a power source that can efficiently inject and extract energy, and an efficient power delivery system to connect the power source to the circuit nodes. The additional circuitry and timing required to support this process can readily exceed the power-savings benefit. Clock-powered logic is a circuit-level, energy-recovery approach that has been implemented in two generations of small-scale microprocessor experiments. The results have shown that it is possible and practical to extract useful amounts of power savings by leveraging the additional circuitry for other compatible purposes. The capabilities and limitations of clock-powered logic as a competitive low-power approach are presented and discussed in this paper.