Practical implementation of charge recovering asymptotically zero power CMOS
Proceedings of the 1993 symposium on Research on integrated systems
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
A true single-phase 8-bit adiabatic multiplier
Proceedings of the 38th annual Design Automation Conference
A 225 MHz resonant clocked ASIC chip
Proceedings of the 2003 international symposium on Low power electronics and design
Two-Phase Resonant Clock Distribution
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A GHz-class charge recovery logic
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
| Hi-index | 0.00 |
In this paper, we propose Boost Logic, a logic family which relies on voltage scaling, gate overdrive, and energy recovery techniques to achieve high energy efficiency at frequencies in the GHz range. The key feature of our design is the use of an energy recovering "boost" stage to provide an efficient gate overdrive to a highly voltage-scaled logic at near-threshold supply voltage. We have evaluated our logic family using simulation results from an 8-bit carry-save multiplier in a 0.13µm CMOS process with V_th=340mV. At 1.4GHz and a 1.1V supply voltage, the Boost multiplier dissipates 3.44pJ per computation, achieving 57% energy savings with respect to its static CMOS counterpart. Using low V_th devices, Boost Logic has been verified to operate at 2GHz with a 1.2V voltage supply and 3.76pJ energy dissipation per cycle.