Practical implementation of charge recovering asymptotically zero power CMOS
Proceedings of the 1993 symposium on Research on integrated systems
Low-power digital systems based on adiabatic-switching principles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
AC-1: a clock-powered microprocessor
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Low Power Digital CMOS Design
Single-phase source-coupled adiabatic logic
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Analysis of power-clocked CMOS with application to the design of energy-recovery circuits
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Theory and practical implementation of harmonic resonant rail driver
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
A resonant clock generator for single-phase adiabatic systems
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
A reversible carry-look-ahead adder using control gates
Integration, the VLSI Journal
A true single-phase energy-recovery multiplier
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy recovery strategy for low power CMOS circuits design
ICECS'03 Proceedings of the 2nd WSEAS International Conference on Electronics, Control and Signal Processing
Energy-efficient low-latency 600 MHz FIR with high-overdrive charge-recovery logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In dynamic logic families that rely on energy recovery to achieve low energy dissipation, the flow of data through cascaded gates is controlled using multi-phase clocks. Consequently, these families require multiple clock generators and can exhibit increased energy consumption on their clock distribution networks. Moreover, they are not attractive for high-speed design due to clock skew management problems.In this paper, we present TSEL, the first energy-recovering logic family that operates with a single-phase clocking scheme. TSEL outperforms previous energy-recovering logic families in terms of energy efficiency and operating speed. In IISPICE simulations with a standard 0.5µm technology from MOSIS, pipelined carry-lookahead adders in TSEL function correctly for operating frequencies exceeding 280MHz. For operating frequencies above 80MHz, they dissipate considerably less energy per operation than alternative implementations of the same adder architecture in other energy-recovering logic families. In comparison with their CMOS counterparts, the TSEL adders dissipate about half as much energy at 280MHz. Our results indicate that TSEL is an excellent candidate for high speed and low power VLSI system design.