Electroid-oriented adiabatic switching circuits
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Signal entropy and the thermodynamics of computation
IBM Systems Journal
Lower bounds on power dissipation for DSP algorithms
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Comparison of high speed voltage-scaled conventional and adiabatic circuits
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Quasi-static energy recovery logic and supply-clock generation circuits
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Enhanced prediction of energy losses during adiabatic charging
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
AC-1: a clock-powered microprocessor
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
True single-phase energy-recovering logic for low-power, high-speed VLSI
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
A three-port adiabatic register file suitable for embedded applications
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Low-Power Design for Real-Time Systems
Real-Time Systems
Retractile clock-powered logic
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Ultra-low power digital subthreshold logic circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Single-phase source-coupled adiabatic logic
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Digital CMOS logic operation in the sub-threshold region
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
A three-port nRERL register file for ultra-low-energy applications
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Analysis of power-clocked CMOS with application to the design of energy-recovery circuits
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A Single Clocked Adiabatic Static Logic—A Proposal for Digital Low Power Applications
Journal of VLSI Signal Processing Systems
A true single-phase 8-bit adiabatic multiplier
Proceedings of the 38th annual Design Automation Conference
A resonant clock generator for single-phase adiabatic systems
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Power estimation in adiabatic circuits: a simple and accurate model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy Efficient Adiabatic Multiplier-Accumulator Design
Journal of VLSI Signal Processing Systems
A Number System with Continuous Valued Digits and Modulo Arithmetic
IEEE Transactions on Computers
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Design of Reversible Logic Circuits by Means of Control Gates
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Resonant Multistage Charging of Dominant Capacitances
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
A hybrid adiabatic content addressable memory for ultra low-power applications
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Energy recovery for low-power CMOS
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Power Optimization of Delay Constrained CMOS Bus Drivers
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A 225 MHz resonant clocked ASIC chip
Proceedings of the 2003 international symposium on Low power electronics and design
Energy recovery clocking scheme and flip-flops for ultra low-energy applications
Proceedings of the 2003 international symposium on Low power electronics and design
A true single-phase energy-recovery multiplier
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Voltage-pulse driven harmonic resonant rail drivers for low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
On optimality of adiabatic switching in MOS energy-recovery circuit
Proceedings of the 2004 international symposium on Low power electronics and design
On optimality of adiabatic switching in MOS energy-recovery circuit
Proceedings of the 2004 international symposium on Low power electronics and design
Evaluation of energy consumption in RC ladder circuits driven by a ramp input
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy recovery clocked dynamic logic
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Charge-Recovery Computing on Silicon
IEEE Transactions on Computers
Ultralow-power adiabatic circuit semi-custom design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Introduction to reversible computing: motivation, progress, and challenges
Proceedings of the 2nd conference on Computing frontiers
Implementation of a simple 8-bit microprocessor with reversible energy recovery logic
Proceedings of the 2nd conference on Computing frontiers
Two-Phase Resonant Clock Distribution
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Optimization of circuit trajectories: an auxiliary network approach
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Elmore model for energy estimation in RC trees
Proceedings of the 43rd annual Design Automation Conference
Reversible P Systems to Simulate Fredkin Circuits
Fundamenta Informaticae - SPECIAL ISSUE MCU2004
A novel charge recycling design scheme based on adiabatic charge pump
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ICECS'03 Proceedings of the 2nd WSEAS International Conference on Electronics, Control and Signal Processing
Energy recovery strategy for low power CMOS circuits design
ICECS'03 Proceedings of the 2nd WSEAS International Conference on Electronics, Control and Signal Processing
SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Dual-rail transition logic: A logic style for counteracting power analysis attacks
Computers and Electrical Engineering
Custom topology rotary clock router with tree subnetworks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2009 conference on Information Science, Technology and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Two phase clocked adiabatic static CMOS logic
SOC'09 Proceedings of the 11th international conference on System-on-chip
Improving the energy efficiency of reversible logic circuits by the combined use of adiabatic styles
Integration, the VLSI Journal
Energy consumption in RC tree circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ultra low-power clocking scheme using energy recovery and clock gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power consumption in reversible logic addressed by a ramp voltage
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Reversible P Systems to Simulate Fredkin Circuits
Fundamenta Informaticae - SPECIAL ISSUE MCU2004
Energy-efficient low-latency 600 MHz FIR with high-overdrive charge-recovery logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RMDDS: Reed-muller decision diagram synthesis of reversible logic circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Hi-index | 0.01 |
Adiabatic switching is an approach to low-power digital circuits that differs fundamentally from other practical low-power techniques. When adiabatic switching is used, the signal energies stored on circuit capacitances may be recycled instead of dissipated as heat. We describe the fundamental adiabatic amplifier circuit and analyze its performance. The dissipation of the adiabatic amplifier is compared to that of conventional switching circuits, both for the case of a fixed voltage swing and the case when the voltage swing can be scaled to reduce power dissipation. We show how combinational and sequential adiabatic-switching logic circuits may be constructed and describe the timing restrictions required for adiabatic operation. Small chip-building experiments have been performed to validate the techniques and to analyse the associated circuit overhead.