Low-power digital systems based on adiabatic-switching principles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Energy recovery for the design of high-speed, low-power static RAMs
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
A three-port adiabatic register file suitable for embedded applications
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
An 8-b nRERL microprocessor for ultra-low-energy applications
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Energy recovering static memory
Proceedings of the 2002 international symposium on Low power electronics and design
Reducing register ports for higher speed and lower energy
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Constant-load energy recovery memory for efficient high-speed operation
Proceedings of the 2004 international symposium on Low power electronics and design
Implementation of a simple 8-bit microprocessor with reversible energy recovery logic
Proceedings of the 2nd conference on Computing frontiers
Complexity reduction in an nRERL microprocessor
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
An integrated heuristic approach to power-aware real-time scheduling
PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
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In this paper, we propose an adiabatic register file for ultra-low-energy applications, which uses a new reversible adiabatic logic, nRERL [1]. The nRERL register file discards garbage information with minimal energy dissipation. We designed a 16x8b three-port nRERL register file. From SPICE simulations, we found that the nRERL register file consumes less than 10% of the energy consumed in the conventional register file at the frequency of lower than 1MHz. We also describe how to design a RAM, a large array of the storage cells