The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Energy recovery for the design of high-speed, low-power static RAMs
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
A three-port adiabatic register file suitable for embedded applications
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
A three-port nRERL register file for ultra-low-energy applications
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A resonant clock generator for single-phase adiabatic systems
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Constant-load energy recovery memory for efficient high-speed operation
Proceedings of the 2004 international symposium on Low power electronics and design
Charge-Recovery Computing on Silicon
IEEE Transactions on Computers
Fast, efficient, recovering, and irreversible
Proceedings of the 2nd conference on Computing frontiers
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This paper proposes an energy-recovering (a.k.a. adiabatic) static RAM with a novel driver that reduces power dissipation by efficiently recovering energy from the bit/word line capacitors. Powered by a single-phase sinusoidal power-clock, our SRAM delivers read and write operations with single-cycle latency. To that end, a precharge-low scheme is employed along with a modified sense amplifier design that achieves high efficiency at differential voltages near $VSS. A simple control circuit is used to maintain driver operation in synchrony with the power-clock waveform. Feedback circuitry from the driver output to the control circuit ensures that our driver remains efficient, independent of the access pattern. Our energy recovering SRAM functions correctly while achieving substantial energy savings over a wide range of supply voltages and operating frequencies. Hspice simulations of a simple full-custom adiabatic 256x256 SRAM, that includes the energy recovering bit/word line drivers, the cell array, and the sense amplifiers, show over 2.6x energy savings at 3V, 300MHz in comparison with its conventional counterpart.