Low-power digital systems based on adiabatic-switching principles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Energy recovery for the design of high-speed, low-power static RAMs
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
A three-port nRERL register file for ultra-low-energy applications
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Energy recovering static memory
Proceedings of the 2002 international symposium on Low power electronics and design
Constant-load energy recovery memory for efficient high-speed operation
Proceedings of the 2004 international symposium on Low power electronics and design
An integrated heuristic approach to power-aware real-time scheduling
PACS'02 Proceedings of the 2nd international conference on Power-aware computer systems
Low-power register file based on adiabatic logic circuits
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Adiabatic logic promises extremely low power consumption for those applications where slower clock rates are acceptable. However, there have been very few adiabatic memory designs, and any circuit of even moderate complexity requires some form of RAM. This paper presents a register file implemented entirely with adiabatic logic, and fabricated using a 1.2 µm CMOS technology. Comparison with a conventional CMOS logic implementation, using both measured and simulated results, indicates significant power savings have been realised.