A three-port adiabatic register file suitable for embedded applications
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
A three-port nRERL register file for ultra-low-energy applications
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Energy recovering static memory
Proceedings of the 2002 international symposium on Low power electronics and design
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Charge-Recovery Computing on Silicon
IEEE Transactions on Computers
Minimizing power dissipation during write operation to register files
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
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This paper proposes a constant-load SRAM design for highly efficient recovery of bit-line energy with a resonant power-clock supply. For each bit-line pair, the proposed SRAM includes a dummy bit-line of sufficient capacitance to ensure that the memory array presents a constant capacitive load to the power-clock, regardless of data or operation. Using a single-phase power-clock waveform, read and write operations are performed with single-cycle latency. The efficiency of the proposed SRAM has been assessed through simulations of 128x256 arrays with 0.25µm process parameters and a 42/58 write/non-write access pattern. Assuming lossless power-clock generation, the proposed SRAM dissipates 37% less power than its conventional counterpart at 400MHz/2.5V. When the overhead of power-clock generation is included, the proposed SRAM dissipates at least 27% less power than conventional SRAM.