MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Low Power SRAM Design using Hierarchical Divided Bit-Line Approach
ICCD '98 Proceedings of the International Conference on Computer Design
A low-power charge-recycling ROM architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Constant-load energy recovery memory for efficient high-speed operation
Proceedings of the 2004 international symposium on Low power electronics and design
A Low-Power SRAM Design Using Quiet-Bitline Architecture
MTDT '05 Proceedings of the 2005 IEEE International Workshop on Memory Technology, Design, and Testing
Charge recycling in MTCMOS circuits: concept and analysis
Proceedings of the 43rd annual Design Automation Conference
A low-power ROM using single charge-sharing capacitor and hierarchical bit line
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a power reduction mechanism for the write operation in register files (RegFiles), which adds a conditional charge-sharing structure to the pair of complementary bit-lines in each column of the RegFile. Because the read and write ports for the RegFile are separately implemented, it is possible to avoid pre-charging the bit-line pair for consecutive writes. More precisely, when writing same values to some cells in the same column of the RegFile, it is possible to eliminate energy consumption due to precharging of the bit-line pair. At the same time, when writing opposite values to some cells in the same column of the RegFile, it is possible to reduce energy consumed in charging the bit-line pair thanks to charge-sharing. Motivated by these observations, we modify the bit-line structure of the write ports in the RegFile such that i) we remove per-cycle bitline pre-charging and ii) we employ conditional data dependent charge-sharing. Experimental results on a set of SPEC2000INT / MediaBench benchmarks show an average of 61.5% energy savings with 5.1% area overhead and 16.2% increase in write access delay.